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個人檔案
教育/學術資格
PhD, 電子, 國立陽明交通大學
指紋
查看啟用 Yao-Jen Lee 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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過去五年中的合作和熱門研究領域
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整合水平與垂直電晶體之次二奈米技術節點L型互補式場效電晶體(L-CFET)的製作與設計
Lee, Y.-J. (PI)
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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臺日(JP)雙邊協議型擴充加值(add-on) 國際合作研究計畫－應用於AI晶片技術的三維異質功能性互補式場效電晶體 (hCFETs)
Lee, Y.-J. (PI)
1/04/22 → 31/03/23
研究計畫: Other Government Ministry Institute
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Design and Simulation of Long-Retention Capacitorless 1T-DRAM Using Experimentally Calibrated Process and Device Simulations
Cheng, S. H., Wang, C. H., Hsu, F. C., Lee, Y.-J. & Li, Y., 2026, Proceedings of the 27th International Symposium on Quality Electronic Design, ISQED 2026. IEEE Computer Society, (Proceedings - International Symposium on Quality Electronic Design, ISQED).研究成果: Conference contribution › 同行評審
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Damage-Free Neutral Beam Etching for Gate Recess in E-Mode AlGaN/GaN HEMTs
Chen, Y. H., Chu, F. C., Aslam, M., Lee, Y.-J., Li, Y. & Samukawa, S., 2025, 於: IEEE Electron Device Letters. 46, 5, p. 705-708 4 p.研究成果: Article › 同行評審
7 引文 斯高帕斯（Scopus） -
DC-free Method to Evaluate Nanoscale Equivalent Oxide Thickness: Dark-Mode Scanning Capacitance Microscopy
Chang, M. N., Wu, Y. S., Lin, C. J., Hsueh, Y. H., Su, C. J. & Lee, Y. J., 6月 2024, 於: Nanomaterials. 14, 11, 934.研究成果: Article › 同行評審
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Heterogeneous CFET: A Pathway to CMOS Performance Balance Engineering
Yu, X. R., Lu, W. H., Chang, S. W., Chang, W. H., Lu, D. D., Lee, Y.-J., Maeda, T., Wu, W. F., Li, Y. M. & Wang, Y. H., 2024, 2024 IEEE Silicon Nanoelectronics Workshop, SNW 2024. Institute of Electrical and Electronics Engineers Inc., p. 5-6 2 p. (2024 IEEE Silicon Nanoelectronics Workshop, SNW 2024).研究成果: Conference contribution › 同行評審
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Investigation on Germanium Transistors with HfOx-Based Gate Stacks for CMOS Operations
Hong, T. C., Su, C. J., Lee, Y.-J., Li, Y., Samukawa, S. & Chao, T. S., 1月 2024, 於: ECS Journal of Solid State Science and Technology. 13, 1, 015005.研究成果: Article › 同行評審
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