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Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology
Ming-Dou Ker
, Hsin Chin Jiang
研究成果
:
Conference contribution
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同行評審
9
引文 斯高帕斯(Scopus)
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Keyphrases
Electrostatic Discharge (ESD) Protection
100%
Nanotechnology
100%
CMOS Integrated Circuits
100%
Protection Strategy
100%
Electrostatic Discharge
83%
Nanoscale CMOS
50%
Protection Circuit
33%
CMOS Devices
33%
CMOS IC
33%
Interface Circuit
33%
Internal Electrostatic Discharge
33%
On chip
16%
Integrated Circuits
16%
Novel Design
16%
Circuit Techniques
16%
Design Concept
16%
Reliability Issues
16%
Power Lines
16%
Downscaling
16%
IC chip
16%
Electrostatic Discharge Current
16%
Protection Solutions
16%
Engineering
Electrostatic Discharge
100%
CMOS Integrated Circuits
100%
Protection Strategy
100%
Internals
28%
Nanoscale
21%
Interface Circuit
14%
Design Concept
7%
Power Line
7%
Integrated Circuit
7%