TY - JOUR
T1 - Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins
AU - Ker, Ming-Dou
AU - Chang, Hun Hsien
PY - 1999/1/1
Y1 - 1999/1/1
N2 - A novel whole-chip ESD (electrostatic discharge) protection design with multiple ESD buses has been proposed to solve the ESD protection issue in the CMOS IC which has multiple mixed-voltage power pins. The ESD current in the CMOS IC is diverted into the ESD buses, therefore the ESD current is conducted by the ESD buses away from the internal circuits and quickly discharged through the desired ESD protection devices. By using the ESD buses, the CMOS IC with separated power pins can be safety protected against the ESD damages which is often located in the internal circuits.
AB - A novel whole-chip ESD (electrostatic discharge) protection design with multiple ESD buses has been proposed to solve the ESD protection issue in the CMOS IC which has multiple mixed-voltage power pins. The ESD current in the CMOS IC is diverted into the ESD buses, therefore the ESD current is conducted by the ESD buses away from the internal circuits and quickly discharged through the desired ESD protection devices. By using the ESD buses, the CMOS IC with separated power pins can be safety protected against the ESD damages which is often located in the internal circuits.
UR - http://www.scopus.com/inward/record.url?scp=0032599125&partnerID=8YFLogxK
U2 - 10.1109/VTSA.1999.786059
DO - 10.1109/VTSA.1999.786059
M3 - Conference article
AN - SCOPUS:0032599125
SN - 1524-766X
SP - 298
EP - 301
JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
T2 - Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications
Y2 - 7 June 1999 through 10 June 1999
ER -