Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

Ming-Dou Ker; Chung-Yu Wu; Hun Hsien Chang; Tain Shun Wu

doi:10.1109/CICC.1997.606579

Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

Ming-Dou Ker^*, Chung-Yu Wu, Hun Hsien Chang, Tain Shun Wu

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

15 引文斯高帕斯（Scopus）

摘要

A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an 8-bits DAC chip in a 0.6-μm CMOS process with a pin-to-pin ESD robustness of above 4 KV.

原文	English
頁（從 - 到）	31-34
頁數	4
期刊	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1997.606579
出版狀態	Published - 1997
事件	Proceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA 持續時間: 5 5月 1997 → 8 5月 1997

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10.1109/CICC.1997.606579

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title = "Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology",

abstract = "A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an 8-bits DAC chip in a 0.6-μm CMOS process with a pin-to-pin ESD robustness of above 4 KV.",

author = "Ming-Dou Ker and Chung-Yu Wu and Chang, {Hun Hsien} and Wu, {Tain Shun}",

year = "1997",

doi = "10.1109/CICC.1997.606579",

language = "English",

pages = "31--34",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1997 IEEE Custom Integrated Circuits Conference ; Conference date: 05-05-1997 Through 08-05-1997",

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T1 - Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Chang, Hun Hsien

AU - Wu, Tain Shun

PY - 1997

Y1 - 1997

N2 - A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an 8-bits DAC chip in a 0.6-μm CMOS process with a pin-to-pin ESD robustness of above 4 KV.

AB - A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an 8-bits DAC chip in a 0.6-μm CMOS process with a pin-to-pin ESD robustness of above 4 KV.

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U2 - 10.1109/CICC.1997.606579

DO - 10.1109/CICC.1997.606579

M3 - Conference article

AN - SCOPUS:0030709080

SN - 0886-5930

SP - 31

EP - 34

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the 1997 IEEE Custom Integrated Circuits Conference

Y2 - 5 May 1997 through 8 May 1997

ER -

Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

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