Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

Keyphrases

• ESD Protection 100%
• ESD Failure 100%
• CMOS VLSI 100%
• Power Supply 50%
• Experimental Verification 50%
• CMOS IC 50%
• Anomalous Events 50%

Engineering

• Power Supply 100%
• Supply Pin 100%