Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

Ming-Dou Ker; Chung-Yu Wu; Tao Cheng; Michael J.N. Wu; T. L. Yu; Alex C. Wang

doi:10.1109/IRWS.1994.515839

Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

Ming-Dou Ker^*, Chung-Yu Wu, Tao Cheng, Michael J.N. Wu, T. L. Yu, Alex C. Wang

^*此作品的通信作者

電子研究所

研究成果: Paper › 同行評審

9 引文斯高帕斯（Scopus）

摘要

An anomalous phenomenon of ESD failure in CMOS ICs with multiple VDD and VSS power-supply pins is discovered and investigated. A method of whole-chip ESD protection to overcome this anomalous ESD failure is proposed with experimental verification.

原文	English
頁面	124-128
頁數	5
DOIs	https://doi.org/10.1109/IRWS.1994.515839
出版狀態	Published - 1994
事件	Proceedings of the 1994 International Integrated Reliability Workshop Final Report - Lake Tahoe, CA, USA 持續時間: 16 10月 1994 → 19 10月 1994

Conference

Conference	Proceedings of the 1994 International Integrated Reliability Workshop Final Report
城市	Lake Tahoe, CA, USA
期間	16/10/94 → 19/10/94

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10.1109/IRWS.1994.515839

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@conference{d7b5299f604649bd877a4ce35fb20f0e,

title = "Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins",

abstract = "An anomalous phenomenon of ESD failure in CMOS ICs with multiple VDD and VSS power-supply pins is discovered and investigated. A method of whole-chip ESD protection to overcome this anomalous ESD failure is proposed with experimental verification.",

author = "Ming-Dou Ker and Chung-Yu Wu and Tao Cheng and Wu, {Michael J.N.} and Yu, {T. L.} and Wang, {Alex C.}",

year = "1994",

doi = "10.1109/IRWS.1994.515839",

language = "English",

pages = "124--128",

note = "Proceedings of the 1994 International Integrated Reliability Workshop Final Report ; Conference date: 16-10-1994 Through 19-10-1994",

}

TY - CONF

T1 - Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Cheng, Tao

AU - Wu, Michael J.N.

AU - Yu, T. L.

AU - Wang, Alex C.

PY - 1994

Y1 - 1994

N2 - An anomalous phenomenon of ESD failure in CMOS ICs with multiple VDD and VSS power-supply pins is discovered and investigated. A method of whole-chip ESD protection to overcome this anomalous ESD failure is proposed with experimental verification.

AB - An anomalous phenomenon of ESD failure in CMOS ICs with multiple VDD and VSS power-supply pins is discovered and investigated. A method of whole-chip ESD protection to overcome this anomalous ESD failure is proposed with experimental verification.

UR - http://www.scopus.com/inward/record.url?scp=0028736733&partnerID=8YFLogxK

U2 - 10.1109/IRWS.1994.515839

DO - 10.1109/IRWS.1994.515839

M3 - Paper

AN - SCOPUS:0028736733

SP - 124

EP - 128

T2 - Proceedings of the 1994 International Integrated Reliability Workshop Final Report

Y2 - 16 October 1994 through 19 October 1994

ER -

Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

摘要

Conference

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