Whole-chip ESD protection design for submicron CMOS VLSI

Ming-Dou Ker; Shue Chang Liu

doi:10.1109/ISCAS.1997.621526

Whole-chip ESD protection design for submicron CMOS VLSI

Ming-Dou Ker^*, Shue Chang Liu

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

10 引文斯高帕斯（Scopus）

摘要

A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC's. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 KV.

原文	English
頁（從 - 到）	1920-1923
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	3
DOIs	https://doi.org/10.1109/ISCAS.1997.621526
出版狀態	Published - 1997
事件	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong 持續時間: 9 6月 1997 → 12 6月 1997

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10.1109/ISCAS.1997.621526

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title = "Whole-chip ESD protection design for submicron CMOS VLSI",

abstract = "A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC's. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 KV.",

author = "Ming-Dou Ker and Liu, {Shue Chang}",

year = "1997",

doi = "10.1109/ISCAS.1997.621526",

language = "English",

volume = "3",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) ; Conference date: 09-06-1997 Through 12-06-1997",

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AU - Ker, Ming-Dou

AU - Liu, Shue Chang

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AB - A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC's. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 KV.

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U2 - 10.1109/ISCAS.1997.621526

DO - 10.1109/ISCAS.1997.621526

M3 - Conference article

AN - SCOPUS:0030655083

SN - 0271-4310

VL - 3

SP - 1920

EP - 1923

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)

Y2 - 9 June 1997 through 12 June 1997

ER -

Whole-chip ESD protection design for submicron CMOS VLSI

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