Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies

Ming Fang Lai, Shih Wei Li, Jian Yu Shih, Kuan-Neng Chen*

*此作品的通信作者

研究成果: Review article同行評審

24 引文 斯高帕斯(Scopus)

摘要

Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.

原文English
頁(從 - 到)3282-3286
頁數5
期刊Microelectronic Engineering
88
發行號11
DOIs
出版狀態Published - 1 十一月 2011

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