Wafer-level 3D integration technology

Steven J. Koester*, Albert M. Young, Roy R. Yu, Sampath Purushothaman, Kuan-Neng Chen, Douglas C. La Tulipe, Narender Rana, Leathen Shi, Matthew R. Wordeman, Edmund J. Sprogis

*此作品的通信作者

研究成果: Review article同行評審

137 引文 斯高帕斯(Scopus)

摘要

An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.

原文English
頁(從 - 到)583-597
頁數15
期刊IBM Journal of Research and Development
52
發行號6
DOIs
出版狀態Published - 1 一月 2008

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