A high-speed image compression VLSI processor based on the systolic architecture of difference-codebook binary tree-searched vector quantization has been developed to meet the increasing demands on large-voiume data communication and storage requirements. Simulation results show that this design is applicable to many types of image data and capable of producing good reconstructed data quality at high compression ratios. Various design aspects of the binary tree-searched vector quantizer including the algorithm, architecture, and detailed functional design are thoroughly investigated for VLSI implementation. An 8-Ievel difference-codebook binary tree-searched vector quantizer can be implemented on a custom VLSI chip that includes a systolic array of eight identical processors and a hierarchical memory of eight subcodebook memory banks. The total transistor count is about 300 000 and the die size is about 8.67 x 7.72 mm2in a 1.0 mm CMOS technology. The throughput rate of this high-speed VLSI compression system is approximately 25 M pixels per second and its equivalent computation power is 600 million instructions per second.
|頁（從 - 到）
|IEEE Transactions on Very Large Scale Integration (VLSI) Systems
|Published - 1 1月 1994