VLSI Neuroprocessors for Video Motion Detection

Ji Chien Lee, Bing J. Sheu, Wai-Chi Fang, Rama Chellappa

研究成果: Article同行評審

15 引文 斯高帕斯(Scopus)


The system design of a locally connected competitive neural network for video motion detection is presented. The motion information from a sequence of image data can be determined through a two-dimensional multiprocessor array in which each processing element consists of an analog neuroprocessor. Massively parallel neurocomputing is done by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is performed by using an analog point-to-point interconnection scheme. To maintain strong signal strength over the whole system, global data communication between the host computer and neuroprocessors is carried out in a digital common bus. A mixed-signal very large scale integration (VLSI) neural chip that includes multiple neuroprocessors for fast video motion detection has been developed. Measured results of the programmable synapse, and winner-take-all circuitry are presented. Based on the measurement data, system-level analysis on a sequence of real-world images was conducted. A 1.5 x 2.8-cm chip in a 1.2-μm CMOS technology can accommodate 64 velocity-selective neuroprocessors. Each chip can achieve 83.2 giga connections per second. The intrinsic speed-up factor over a Sun-4/75 workstation is around 180.

頁(從 - 到)178-191
期刊IEEE Transactions on Neural Networks
出版狀態Published - 1 1月 1993


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