VLSI implementation of an ultra-low-cost and low-power image compressor for wireless camera networks

In this paper, a novel hardware-oriented color image compression algorithm based on digital halftoning and block truncation coding (BTC) techniques is proposed for very large-scale integration (VLSI) implementation. The proposed technique consists of a threshold generator, a bitmap generator, a BTC training module, a predictor, and a signed Golomb–Rice coding module. Because the wireless camera network is developed for perceiving, measuring, and collecting information from the environment, each camera sensing node should be designed to achieve low cost, small size, high compression rates, and low power consumption. Hence, a novel low-complexity, high-performance, transform-free, hardware-oriented color image compression algorithm based on digital halftoning and BTC is proposed. In order to achieve the performance of compressing images in real time, the proposed color image compression algorithm was realized by a VLSI technique. The VLSI architecture in this work contains only 8.1-k gate counts, and the core area is 81,000 μm² synthesized using a TSMC 0.18-μm CMOS process. The operating frequency of this work is 100 MHz and consumes 2.91 mW, which is efficient to develop wireless electronic systems with the demand of color image compression in real time. Compared with JPEG- and JPEG-LS-based designs, this work reduces gate counts by at least 71.1 % and power consumption by 53 % and only requires a one-line-buffer memory.