跳至主導覽
跳至搜尋
跳過主要內容
國立陽明交通大學研發優勢分析平台 首頁
English
中文
首頁
人員
單位
研究成果
計畫
獎項
活動
貴重儀器
影響
按專業知識、姓名或所屬機構搜尋
VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems
Yuan Ho Chen
*
, Hsin Tung Hua,
Chin Fu Nien
, Shinn Yn Lin
*
此作品的通信作者
電機工程學系
研究成果
:
Article
›
同行評審
總覽
指紋
指紋
深入研究「VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems」主題。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Annealing
100%
VLSI Implementation
100%
Combinatorial Optimization Problem
100%
Complementary Metal-oxide-semiconductor Technology
66%
Ising Model
66%
Taiwan
33%
Excellent Performance
33%
Fully Connected
33%
Semiconductor Manufacturing
33%
Power Consumption
33%
Area Consumption
33%
Manufacturing Firms
33%
Complementary Metal Oxide Semiconductor
33%
Hardware Architecture
33%
Pseudorandom number Generator
33%
Quantum Computing
33%
Formulation Optimization
33%
Economic Constraints
33%
Multiple Solutions
33%
Temperature Constraint
33%
Quantum Annealing
33%
Traditional Computing
33%
Multiple Mappings
33%
Quadratic Unconstrained Binary Optimization
33%
Quantum Computing Algorithms
33%
Semiconductor Annealing
33%
Engineering
Optimisation Problem
100%
Complementary Metal-Oxide-Semiconductor
100%
Ising Model
66%
Quantum Computation
66%
Experimental Result
33%
Semiconductor Manufacturing
33%
Electric Power Utilization
33%
Manufacturing Company
33%
Random Number
33%
Application Field
33%
Computer Science
Combinatorial Optimization Problem
100%
Complementary Metal Oxide Semiconductor
100%
Quantum Computing
66%
Experimental Result
33%
Power Consumption
33%
Hardware Architecture
33%
Optimization Formulation
33%
Circuit Technology
33%
Pseudo-Random Number Generator
33%