TY - GEN
T1 - VLSI focal-plane array processor for morphological image processing
AU - Fang, W. C.
AU - Shaw, T.
AU - Yu, J.
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - A full-custom mixed-signal VLSI design for high-speed morphological image processing is developed by combining a two-dimensional fine-grain parallel array architecture with on-chip focal-plane photodetectors and transmitters. An 8∗8 array processor prototype chip is designed in a 1.2-mm∗1.2-mm silicon area using the MOSIS 2- mu m CMOS process.
AB - A full-custom mixed-signal VLSI design for high-speed morphological image processing is developed by combining a two-dimensional fine-grain parallel array architecture with on-chip focal-plane photodetectors and transmitters. An 8∗8 array processor prototype chip is designed in a 1.2-mm∗1.2-mm silicon area using the MOSIS 2- mu m CMOS process.
UR - http://www.scopus.com/inward/record.url?scp=84893897050&partnerID=8YFLogxK
U2 - 10.1109/ASIC.1992.270255
DO - 10.1109/ASIC.1992.270255
M3 - Conference contribution
AN - SCOPUS:84893897050
T3 - Proceedings of International Conference on ASIC
SP - 423
EP - 426
BT - Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
PB - IEEE Computer Society
T2 - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
Y2 - 21 September 1992 through 25 September 1992
ER -