TY - JOUR
T1 - VLSI design of turbo decoder for integrated communication system-on-chip applications
AU - Fang, Wai-Chi
AU - Sethuram, Ashwin
AU - Belevi, Kemal
PY - 2003/7/14
Y1 - 2003/7/14
N2 - A high-throughput low-power turbo decoder core has been developed for integrated communication system applications such as Digital Video Broadcast (DVB), satellite communications, wireless LAN, digital TV, cable modem, and xDSL systems. The turbo decoder is based on convolutional constituent codes, which outperform all other Forward Error Correction techniques. This turbo decoder core is parameterizable and can be modified easily to fit any size for advanced communication system-on-chip products. The turbo decoder core provides Forward Error Correction of up to 15 Mbits/sec on a 0.13-micron CMOS FPGA prototyping chip at a power of 0.1 watt.
AB - A high-throughput low-power turbo decoder core has been developed for integrated communication system applications such as Digital Video Broadcast (DVB), satellite communications, wireless LAN, digital TV, cable modem, and xDSL systems. The turbo decoder is based on convolutional constituent codes, which outperform all other Forward Error Correction techniques. This turbo decoder core is parameterizable and can be modified easily to fit any size for advanced communication system-on-chip products. The turbo decoder core provides Forward Error Correction of up to 15 Mbits/sec on a 0.13-micron CMOS FPGA prototyping chip at a power of 0.1 watt.
UR - http://www.scopus.com/inward/record.url?scp=0037746734&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2003.1205907
DO - 10.1109/ISCAS.2003.1205907
M3 - Conference article
AN - SCOPUS:0037746734
SN - 0271-4310
VL - 2
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
Y2 - 25 May 2003 through 28 May 2003
ER -