@inproceedings{9feb7e42469c4323a515bf688334c100,
title = "VLSI design of the shuffle-exchange network for 2D fast transforms",
abstract = "A pipelined shuffle-exchange network is proposed as a generalized 2D orthogonal transforms with flexible transform lengths. The 16×16 points 2-D DCT processor is chosen as the target design for its applicability in video processing. It is constructed in a modulized radix-4 pipelined structure and is implemented with high data rate and low hardware cost. According to the circuit simulations with 1.2 μm standard cell technology, the processing throughput of this DCT circuit can be 40 MHz. Extensibility for various indices and transform lengths is also discussed. Besides, a number of orthogonal transform algorithms are also implemented in the shuffle-exchange network with the same throughput rate.",
author = "Kuei-Ann Wen and Cheng, {Po Wen} and Lin, {Ru Yeong}",
year = "1993",
month = jan,
day = "1",
doi = "10.1109/ISCAS.1993.393831",
language = "English",
isbn = "0780312813",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Publ by IEEE",
pages = "754--757",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
note = "null ; Conference date: 03-05-1993 Through 06-05-1993",
}