VLSI architecture design of VLC encoder for high data rate video/image coding

Hao Chieh Chang*, Liang Gee Chen, Yung Chi Chang, Sheng-Chieh Huang

*此作品的通信作者

研究成果: Conference article同行評審

12 引文 斯高帕斯(Scopus)

摘要

An efficient architecture of variable length coding (VLC) is developed for recently multimedia applications, such as video and image compression. VLC plays a crucial part in these applications in that it provides a very effective coding gain. In this paper, we will describe an architecture design of VLC encoder. It can produce VLC codeword and amplitude, and pack them in order to achieve the constant word-length output. In addition, in this pipeline architecture, the VLC codeword and the amplitude can be processed in one clock cycle such that the input data rate of VLC encoder can reach as high as the sampling rate of video/image data. Therefore, it is very suitable for very high data rate video and image compression applications.

原文English
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
DOIs
出版狀態Published - 1 1月 1999
事件Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA
持續時間: 30 5月 19992 6月 1999

指紋

深入研究「VLSI architecture design of VLC encoder for high data rate video/image coding」主題。共同形成了獨特的指紋。

引用此