VLSI architecture design of VLC encoder for high data rate video/image coding

Hao Chieh Chang; Liang Gee Chen; Yung Chi Chang; Sheng-Chieh Huang

doi:10.1109/ISCAS.1999.780026

VLSI architecture design of VLC encoder for high data rate video/image coding

Hao Chieh Chang^*, Liang Gee Chen, Yung Chi Chang, Sheng-Chieh Huang

^*此作品的通信作者

電機工程學系

研究成果: Conference article › 同行評審

12 引文斯高帕斯（Scopus）

摘要

An efficient architecture of variable length coding (VLC) is developed for recently multimedia applications, such as video and image compression. VLC plays a crucial part in these applications in that it provides a very effective coding gain. In this paper, we will describe an architecture design of VLC encoder. It can produce VLC codeword and amplitude, and pack them in order to achieve the constant word-length output. In addition, in this pipeline architecture, the VLC codeword and the amplitude can be processed in one clock cycle such that the input data rate of VLC encoder can reach as high as the sampling rate of video/image data. Therefore, it is very suitable for very high data rate video and image compression applications.

原文	English
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	4
DOIs	https://doi.org/10.1109/ISCAS.1999.780026
出版狀態	Published - 1 1月 1999
事件	Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA 持續時間: 30 5月 1999 → 2 6月 1999

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10.1109/ISCAS.1999.780026

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title = "VLSI architecture design of VLC encoder for high data rate video/image coding",

abstract = "An efficient architecture of variable length coding (VLC) is developed for recently multimedia applications, such as video and image compression. VLC plays a crucial part in these applications in that it provides a very effective coding gain. In this paper, we will describe an architecture design of VLC encoder. It can produce VLC codeword and amplitude, and pack them in order to achieve the constant word-length output. In addition, in this pipeline architecture, the VLC codeword and the amplitude can be processed in one clock cycle such that the input data rate of VLC encoder can reach as high as the sampling rate of video/image data. Therefore, it is very suitable for very high data rate video and image compression applications.",

author = "Chang, {Hao Chieh} and Chen, {Liang Gee} and Chang, {Yung Chi} and Sheng-Chieh Huang",

year = "1999",

month = jan,

day = "1",

doi = "10.1109/ISCAS.1999.780026",

language = "English",

volume = "4",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 30-05-1999 Through 02-06-1999",

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T1 - VLSI architecture design of VLC encoder for high data rate video/image coding

AU - Chang, Hao Chieh

AU - Chen, Liang Gee

AU - Chang, Yung Chi

AU - Huang, Sheng-Chieh

PY - 1999/1/1

Y1 - 1999/1/1

N2 - An efficient architecture of variable length coding (VLC) is developed for recently multimedia applications, such as video and image compression. VLC plays a crucial part in these applications in that it provides a very effective coding gain. In this paper, we will describe an architecture design of VLC encoder. It can produce VLC codeword and amplitude, and pack them in order to achieve the constant word-length output. In addition, in this pipeline architecture, the VLC codeword and the amplitude can be processed in one clock cycle such that the input data rate of VLC encoder can reach as high as the sampling rate of video/image data. Therefore, it is very suitable for very high data rate video and image compression applications.

AB - An efficient architecture of variable length coding (VLC) is developed for recently multimedia applications, such as video and image compression. VLC plays a crucial part in these applications in that it provides a very effective coding gain. In this paper, we will describe an architecture design of VLC encoder. It can produce VLC codeword and amplitude, and pack them in order to achieve the constant word-length output. In addition, in this pipeline architecture, the VLC codeword and the amplitude can be processed in one clock cycle such that the input data rate of VLC encoder can reach as high as the sampling rate of video/image data. Therefore, it is very suitable for very high data rate video and image compression applications.

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U2 - 10.1109/ISCAS.1999.780026

DO - 10.1109/ISCAS.1999.780026

M3 - Conference article

AN - SCOPUS:18344407513

VL - 4

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

Y2 - 30 May 1999 through 2 June 1999

ER -

VLSI architecture design of VLC encoder for high data rate video/image coding

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