VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders

Yiteh Yi Wang*, Yan Tsung Peng, Chun-Jen Tsai

*此作品的通信作者

研究成果: Conference article同行評審

8 引文 斯高帕斯(Scopus)

摘要

In this paper, a new complexity-reduced method and its hardware architecture for motion estimation and the in-loop filter for MPEG-4 AVC/H.264 is proposed. The feature of the proposed method is focused on the computation reduction for the motion search algorithm among multiple reference frames and the mode partition determination. Furthermore, to verify the functionality and performance of the proposed hardware design, an emulation board platform, the ARM Integrator, is used for H.264 hardware/software co-development. The experimental results show that the proposed method has excellent performance with little or no degradation of coding efficiency.

原文English
期刊Proceedings - IEEE International Symposium on Circuits and Systems
2
DOIs
出版狀態Published - 7 9月 2004
事件2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
持續時間: 23 5月 200426 5月 2004

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