TY - JOUR
T1 - VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders
AU - Wang, Yiteh Yi
AU - Peng, Yan Tsung
AU - Tsai, Chun-Jen
PY - 2004/9/7
Y1 - 2004/9/7
N2 - In this paper, a new complexity-reduced method and its hardware architecture for motion estimation and the in-loop filter for MPEG-4 AVC/H.264 is proposed. The feature of the proposed method is focused on the computation reduction for the motion search algorithm among multiple reference frames and the mode partition determination. Furthermore, to verify the functionality and performance of the proposed hardware design, an emulation board platform, the ARM Integrator, is used for H.264 hardware/software co-development. The experimental results show that the proposed method has excellent performance with little or no degradation of coding efficiency.
AB - In this paper, a new complexity-reduced method and its hardware architecture for motion estimation and the in-loop filter for MPEG-4 AVC/H.264 is proposed. The feature of the proposed method is focused on the computation reduction for the motion search algorithm among multiple reference frames and the mode partition determination. Furthermore, to verify the functionality and performance of the proposed hardware design, an emulation board platform, the ARM Integrator, is used for H.264 hardware/software co-development. The experimental results show that the proposed method has excellent performance with little or no degradation of coding efficiency.
UR - http://www.scopus.com/inward/record.url?scp=4344601349&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2004.1329230
DO - 10.1109/ISCAS.2004.1329230
M3 - Conference article
AN - SCOPUS:4344601349
SN - 0271-4310
VL - 2
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings
Y2 - 23 May 2004 through 26 May 2004
ER -