VESTA: A Versatile SNN-Based Transformer Accelerator with Unified PEs for Multiple Computational Layers

Ching Yao Chen*, Meng Chieh Chen, Tian Sheuan Chang

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

Spiking Neural Networks (SNNs) and transformers represent two powerful paradigms in neural computation, known for their low power consumption and ability to capture feature dependencies, respectively. However, transformer architectures typically involve multiple types of computational layers, including linear layers for MLP modules and classification heads, convolution layers for tokenizers, and dot product computations for self-attention mechanisms. These diverse operations pose significant challenges for hardware accelerator design, and to our knowledge, there is not yet a hardware solution that leverages spike-form data from SNNs for transformer architectures. In this paper, we introduce VESTA, a novel hardware design that synergizes these technologies, presenting unified Processing Elements (PEs) capable of efficiently performing all three types of computations crucial to transformer structures. VESTA uniquely benefits from the spike-form outputs of the Spike Neuron Layers [1], simplifying multiplication operations by reducing them from handling two 8-bit integers to handling one 8-bit integer and a binary spike. This reduction enables the use of multiplexers in the PE module, significantly enhancing computational efficiency while maintaining the low-power advantage of SNNs. Experimental results show that the core area of VESTA is 0.844 mm2. It operates at 500 MHz and is capable of real-time image classification at 30 fps.

原文English
主出版物標題APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding
發行者Institute of Electrical and Electronics Engineers Inc.
頁面6-10
頁數5
ISBN(電子)9798350378771
DOIs
出版狀態Published - 2024
事件20th IEEE Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, APCCAS and PrimeAsia 2024 - Taipei, 台灣
持續時間: 7 11月 20249 11月 2024

出版系列

名字APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding

Conference

Conference20th IEEE Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, APCCAS and PrimeAsia 2024
國家/地區台灣
城市Taipei
期間7/11/249/11/24

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