Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Chris Chun Chih Chung, Chiuan Huei Shen, Jer Yi Lin, Chun Chieh Chin, Tien-Sheng Chao*

*此作品的通信作者

研究成果: Article同行評審

16 引文 斯高帕斯(Scopus)

摘要

We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- {k} metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.

原文English
文章編號8233410
頁(從 - 到)756-762
頁數7
期刊IEEE Transactions on Electron Devices
65
發行號2
DOIs
出版狀態Published - 1 2月 2018

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