Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Chris Chun Chih Chung; Chiuan Huei Shen; Jer Yi Lin; Chun Chieh Chin; Tien-Sheng Chao

doi:10.1109/TED.2017.2780851

Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Chris Chun Chih Chung, Chiuan Huei Shen, Jer Yi Lin, Chun Chieh Chin, Tien-Sheng Chao^*

^*此作品的通信作者

電子物理學系

研究成果: Article › 同行評審

18 引文斯高帕斯（Scopus）

摘要

We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- {k} metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.

原文	English
文章編號	8233410
頁（從 - 到）	756-762
頁數	7
期刊	IEEE Transactions on Electron Devices
卷	65
發行號	2
DOIs	https://doi.org/10.1109/TED.2017.2780851
出版狀態	Published - 2月 2018

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10.1109/TED.2017.2780851

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引用此

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abstract = "We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- {k} metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.",

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AU - Chin, Chun Chieh

AU - Chao, Tien-Sheng

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AB - We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- {k} metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.

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Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

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