Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin; Pin Hsin Chang; Rong Kun Chang; Ming-Dou Ker; Wen Tai Wang

doi:10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin, Pin Hsin Chang, Rong Kun Chang, Ming-Dou Ker, Wen Tai Wang

研究成果: Conference contribution › 同行評審

2 引文斯高帕斯（Scopus）

摘要

A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

原文	English
主出版物標題	Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	255-258
頁數	4
ISBN（電子）	9781479999286, 9781479999286
DOIs	https://doi.org/10.1109/IPFA.2015.7224380
出版狀態	Published - 25 8月 2015
事件	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, Taiwan 持續時間: 29 6月 2015 → 2 7月 2015

出版系列

名字	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
卷	2015-August

Conference

Conference	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
國家/地區	Taiwan
城市	Hsinchu
期間	29/06/15 → 2/07/15

存取文件

10.1109/IPFA.2015.7224380

其它文件與鏈接

Link to publication in Scopus

引用此

Lin, C. Y., Chang, P. H., Chang, R. K., Ker, M-D., & Wang, W. T. (2015). Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. 於 Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 (頁 255-258). [7224380] (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; 卷 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2015.7224380

Lin, Chun Yu ; Chang, Pin Hsin ; Chang, Rong Kun 等. / Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 頁 255-258 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{a36ded8ab9874ddcae10b5cfbf2dbbc8,

title = "Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology",

abstract = "A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.",

author = "Lin, {Chun Yu} and Chang, {Pin Hsin} and Chang, {Rong Kun} and Ming-Dou Ker and Wang, {Wen Tai}",

year = "2015",

month = aug,

day = "25",

doi = "10.1109/IPFA.2015.7224380",

language = "English",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "255--258",

booktitle = "Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015",

address = "United States",

note = "22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 ; Conference date: 29-06-2015 Through 02-07-2015",

}

Lin, CY, Chang, PH, Chang, RK, Ker, M-D & Wang, WT 2015, Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. 於 Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015., 7224380, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 卷 2015-August, Institute of Electrical and Electronics Engineers Inc., 頁 255-258, 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015, Hsinchu, Taiwan, 29/06/15. https://doi.org/10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. / Lin, Chun Yu; Chang, Pin Hsin; Chang, Rong Kun 等.
Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 255-258 7224380 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; 卷 2015-August).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

AU - Lin, Chun Yu

AU - Chang, Pin Hsin

AU - Chang, Rong Kun

AU - Ker, Ming-Dou

AU - Wang, Wen Tai

PY - 2015/8/25

Y1 - 2015/8/25

N2 - A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

AB - A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

UR - http://www.scopus.com/inward/record.url?scp=84949811797&partnerID=8YFLogxK

U2 - 10.1109/IPFA.2015.7224380

DO - 10.1109/IPFA.2015.7224380

M3 - Conference contribution

AN - SCOPUS:84949811797

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

SP - 255

EP - 258

BT - Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015

Y2 - 29 June 2015 through 2 July 2015

ER -

Lin CY, Chang PH, Chang RK, Ker M-D, Wang WT. Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. 於 Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 255-258. 7224380. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

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