Vertical interconnects of microbumps in 3D integration

研究成果: Review article同行評審

43 引文 斯高帕斯(Scopus)

摘要

With the electronics packaging industry shifting increasingly to three-dimensional packaging, microbumps have been adopted as the vertical interconnects between chips. Consequently, solder volumes have decreased dramatically, and the solder thickness has reduced to a range between a few and 10 microns. The solder volume of a microbump is approximately two orders of magnitude smaller than a traditional flip-chip joint. In contrast, the thickness of the under-bump metallization (UBM) remains almost the same as that in flip-chip solder joints. Therefore, many issues concerning materials and reliability of microbumps arise. This article reviews the challenges related to microbump materials for vertical interconnects, including transformation of solder joints into intermetallic (IMC) joints, necking or voiding induced by side wetting/diffusion on the circumference of the UBM, formation of porous Cu3Sn IMCs, early electromigration failures caused by specific orientations of Sn grains, and precipitation of plate-like Ag3Sn IMCs. An alternative way of fabricating vertical interconnects using direct Cu-to-Cu bonding is also discussed.

原文English
頁(從 - 到)257-262
頁數6
期刊MRS Bulletin
40
發行號3
DOIs
出版狀態Published - 10 三月 2015

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