Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch

Chun Yen Chen; Ruei Hong Peng; Jen Chieh Tsai; Yu Chi Kang; Chia Lung Ni; Yi Ting Chen; Ke-Horng Chen; Shih Ming Wang; Ming Wei Lee; Hsin Yu Luo

doi:10.1109/ECCE.2012.6342809

Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch

Chun Yen Chen^*, Ruei Hong Peng, Jen Chieh Tsai, Yu Chi Kang, Chia Lung Ni, Yi Ting Chen, Ke-Horng Chen, Shih Ming Wang, Ming Wei Lee, Hsin Yu Luo

^*此作品的通信作者

電機工程學系

研究成果: Paper › 同行評審

摘要

The proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5μm 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.

原文	American English
頁面	298-301
頁數	4
DOIs	https://doi.org/10.1109/ECCE.2012.6342809
出版狀態	Published - 17 12月 2012
事件	4th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2012 - Raleigh, NC, United States 持續時間: 15 9月 2012 → 20 9月 2012

Conference

Conference	4th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2012
國家/地區	United States
城市	Raleigh, NC
期間	15/09/12 → 20/09/12

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10.1109/ECCE.2012.6342809

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Chen, C. Y., Peng, R. H., Tsai, J. C., Kang, Y. C., Ni, C. L., Chen, Y. T., Chen, K.-H., Wang, S. M., Lee, M. W., & Luo, H. Y. (2012). Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch. 298-301. 論文發表於 4th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2012, Raleigh, NC, United States. https://doi.org/10.1109/ECCE.2012.6342809

@conference{7c2cf2c409074824bb4d38548995ed4e,

title = "Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch",

abstract = "The proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5μm 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.",

keywords = "boundary control mode (BCM), interleaving, no-deadtime ramp generator (NDRG), power factor correction (PFC), variable sampling slope (VSS)",

author = "Chen, {Chun Yen} and Peng, {Ruei Hong} and Tsai, {Jen Chieh} and Kang, {Yu Chi} and Ni, {Chia Lung} and Chen, {Yi Ting} and Ke-Horng Chen and Wang, {Shih Ming} and Lee, {Ming Wei} and Luo, {Hsin Yu}",

year = "2012",

month = dec,

day = "17",

doi = "10.1109/ECCE.2012.6342809",

language = "American English",

pages = "298--301",

note = "4th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2012 ; Conference date: 15-09-2012 Through 20-09-2012",

}

Chen, CY, Peng, RH, Tsai, JC, Kang, YC, Ni, CL, Chen, YT, Chen, K-H, Wang, SM, Lee, MW & Luo, HY 2012, 'Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch', 論文發表於 4th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2012, Raleigh, NC, United States, 15/09/12 - 20/09/12 頁 298-301. https://doi.org/10.1109/ECCE.2012.6342809

Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch. / Chen, Chun Yen; Peng, Ruei Hong; Tsai, Jen Chieh 等.
2012. 298-301 論文發表於 4th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2012, Raleigh, NC, United States.

研究成果: Paper › 同行評審

TY - CONF

T1 - Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch

AU - Chen, Chun Yen

AU - Peng, Ruei Hong

AU - Tsai, Jen Chieh

AU - Kang, Yu Chi

AU - Ni, Chia Lung

AU - Chen, Yi Ting

AU - Chen, Ke-Horng

AU - Wang, Shih Ming

AU - Lee, Ming Wei

AU - Luo, Hsin Yu

PY - 2012/12/17

Y1 - 2012/12/17

N2 - The proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5μm 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.

AB - The proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5μm 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.

KW - boundary control mode (BCM)

KW - interleaving

KW - no-deadtime ramp generator (NDRG)

KW - power factor correction (PFC)

KW - variable sampling slope (VSS)

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DO - 10.1109/ECCE.2012.6342809

M3 - Paper

AN - SCOPUS:84870906911

SP - 298

EP - 301

T2 - 4th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2012

Y2 - 15 September 2012 through 20 September 2012

ER -

Chen CY, Peng RH, Tsai JC, Kang YC, Ni CL, Chen YT 等. Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch. 2012. 論文發表於 4th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2012, Raleigh, NC, United States. doi: 10.1109/ECCE.2012.6342809

Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch

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