Validation of Dynamically Depleted Symmetric BSIM-SOI Compact model for RF SOI T/R Switch Applications

Debashish Nandi*, Chetan Kumar Dabhi, Dinesh Rajasekaran, Naveen Karumuri, Sreenidhi Turuvekere, Balaji Swaminathan, Srikanth Srihari, Anupam Dutta, Chenming Hu, Yogesh Singh Chauhan

*此作品的通信作者

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

In this paper, we present the symmetric BSIM-SOI compact model, tailored for Dynamically Depleted Silicon-on-Insulator (DDSOI) MOSFETs, with a primary focus on optimizing their performance in RF Transmit/Receive (T/R) switch applications. This surface potential-based model offers a comprehensive characterization of device behavior, encompassing both Partial Depletion (PD) and Full Depletion (FD) operation regimes while preserving source-drain symmetry and providing correct representation of higher order harmonics. Experimental validation is performed using advanced SPST RF T/R switch hardware from GlobalFoundries Inc., including detailed performance evaluations of critical parameters, such as On resistance, off capacitance, insertion loss, and isolation.

原文English
主出版物標題IEEE Electron Devices Technology and Manufacturing Conference
主出版物子標題Strengthening the Globalization in Semiconductors, EDTM 2024
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9798350371529
DOIs
出版狀態Published - 2024
事件8th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2024 - Bangalore, 印度
持續時間: 3 3月 20246 3月 2024

出版系列

名字IEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024

Conference

Conference8th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2024
國家/地區印度
城市Bangalore
期間3/03/246/03/24

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