Unified bit-parallel arithmetic processor using redundant binary representation

An addition rule for signed-digit representation (SDR), generalized from the addition rule of redundant binary representation, is proposed which is free from carry-propagation. The MSD (most significant digit)-first multiplication operation is easily devised by incorporating hardware redundancy with the redundancy in this addition rule. By combing the all MSD-first arithmetic operations, a unified arithmetic processor is obtained which can perform division, multiplication, and square-root operations. This unified processor is similar in structure to an array multiplier. It provides three advantages over the conventional arithmetic unit: (1) higher speed, (2) more functional capability, and (3) better area utilization. It is also suitable for VLSI implementation.