Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution
- Ming-Dou Ker*
- , Cheng Cheng Yen
*此作品的通信作者
研究成果: Conference contribution › 同行評審
7
引文
斯高帕斯(Scopus)