TY - GEN
T1 - Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution
AU - Ker, Ming-Dou
AU - Yen, Cheng Cheng
PY - 2007/12/1
Y1 - 2007/12/1
N2 - Four different on-chip power-rail electrostatic discharge (ESD) clamp circuits have been designed to investigate their susceptibility to electrical fast transient (EFT) test. From the experimental results, the feedback loop in two kinds of on-chip power-rail ESD clamp circuits provides the lock function to perform a latchup-like failure after the EFT test. The re-design solution will be developed to overcome this issue to meet the regulation of EFT/EMC test.
AB - Four different on-chip power-rail electrostatic discharge (ESD) clamp circuits have been designed to investigate their susceptibility to electrical fast transient (EFT) test. From the experimental results, the feedback loop in two kinds of on-chip power-rail ESD clamp circuits provides the lock function to perform a latchup-like failure after the EFT test. The re-design solution will be developed to overcome this issue to meet the regulation of EFT/EMC test.
UR - http://www.scopus.com/inward/record.url?scp=47149100335&partnerID=8YFLogxK
U2 - 10.1109/EMCZUR.2007.4388198
DO - 10.1109/EMCZUR.2007.4388198
M3 - Conference contribution
AN - SCOPUS:47149100335
SN - 9783952328606
T3 - Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC
SP - 69
EP - 72
BT - Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC
T2 - 18th International Zurich Symposium on Electromagnetic Compatibility, EMC
Y2 - 24 September 2007 through 28 September 2007
ER -