Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension

Li Jen Hsien; Yi Lin Chan; Tien-Sheng Chao; Yeu Long Jiang; Chung Yuan Kung

doi:10.1143/JJAP.41.4519

Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension

Li Jen Hsien^*, Yi Lin Chan, Tien-Sheng Chao, Yeu Long Jiang, Chung Yuan Kung

^*此作品的通信作者

電子物理學系

研究成果: Article › 同行評審

摘要

Method for forming ultra-shallow p⁺/n is demonstrated for 0.15 μm p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p⁺/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Ω/□.

原文	English
頁（從 - 到）	4519-4520
頁數	2
期刊	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
卷	41
發行號	7 A
DOIs	https://doi.org/10.1143/JJAP.41.4519
出版狀態	Published - 7月 2002

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10.1143/JJAP.41.4519

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title = "Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension",

abstract = "Method for forming ultra-shallow p+/n is demonstrated for 0.15 μm p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p+/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Ω/□.",

keywords = "CMOS, Nitride, Shallow junction",

author = "Hsien, {Li Jen} and Chan, {Yi Lin} and Tien-Sheng Chao and Jiang, {Yeu Long} and Kung, {Chung Yuan}",

year = "2002",

month = jul,

doi = "10.1143/JJAP.41.4519",

language = "English",

volume = "41",

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T1 - Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension

AU - Hsien, Li Jen

AU - Chan, Yi Lin

AU - Chao, Tien-Sheng

AU - Jiang, Yeu Long

AU - Kung, Chung Yuan

PY - 2002/7

Y1 - 2002/7

N2 - Method for forming ultra-shallow p+/n is demonstrated for 0.15 μm p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p+/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Ω/□.

AB - Method for forming ultra-shallow p+/n is demonstrated for 0.15 μm p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p+/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Ω/□.

KW - CMOS

KW - Nitride

KW - Shallow junction

UR - http://www.scopus.com/inward/record.url?scp=0036655950&partnerID=8YFLogxK

U2 - 10.1143/JJAP.41.4519

DO - 10.1143/JJAP.41.4519

M3 - Article

AN - SCOPUS:0036655950

SN - 0021-4922

VL - 41

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EP - 4520

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

IS - 7 A

ER -

Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension

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