Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Po Yen Chiu*, Ming-Dou Ker, Fu Yi Tsai, Yeong Jar Chang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    13 引文 斯高帕斯(Scopus)

    摘要

    A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

    原文English
    主出版物標題2009 IEEE International Reliability Physics Symposium, IRPS 2009
    頁面750-753
    頁數4
    DOIs
    出版狀態Published - 2009
    事件2009 IEEE International Reliability Physics Symposium, IRPS 2009 - Montreal, QC, Canada
    持續時間: 26 4月 200930 4月 2009

    出版系列

    名字IEEE International Reliability Physics Symposium Proceedings
    ISSN(列印)1541-7026

    Conference

    Conference2009 IEEE International Reliability Physics Symposium, IRPS 2009
    國家/地區Canada
    城市Montreal, QC
    期間26/04/0930/04/09

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