Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Po Yen Chiu; Ming-Dou Ker; Fu Yi Tsai; Yeong Jar Chang

doi:10.1109/IRPS.2009.5173343

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Po Yen Chiu^*, Ming-Dou Ker, Fu Yi Tsai, Yeong Jar Chang

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

12 引文斯高帕斯（Scopus）

摘要

A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

原文	English
主出版物標題	2009 IEEE International Reliability Physics Symposium, IRPS 2009
頁面	750-753
頁數	4
DOIs	https://doi.org/10.1109/IRPS.2009.5173343
出版狀態	Published - 12 11月 2009
事件	2009 IEEE International Reliability Physics Symposium, IRPS 2009 - Montreal, QC, Canada 持續時間: 26 4月 2009 → 30 4月 2009

出版系列

名字	IEEE International Reliability Physics Symposium Proceedings
ISSN（列印）	1541-7026

Conference

Conference	2009 IEEE International Reliability Physics Symposium, IRPS 2009
國家/地區	Canada
城市	Montreal, QC
期間	26/04/09 → 30/04/09

存取文件

10.1109/IRPS.2009.5173343

其它文件與鏈接

Link to publication in Scopus

引用此

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title = "Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process",

abstract = "A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.",

keywords = "Electrostatic discharge (ESD), ESD clamp circuit, Gate leakage, Silicon-controlled rectifier (SCR)",

author = "Chiu, {Po Yen} and Ming-Dou Ker and Tsai, {Fu Yi} and Chang, {Yeong Jar}",

year = "2009",

month = nov,

day = "12",

doi = "10.1109/IRPS.2009.5173343",

language = "English",

isbn = "0780388038",

series = "IEEE International Reliability Physics Symposium Proceedings",

pages = "750--753",

booktitle = "2009 IEEE International Reliability Physics Symposium, IRPS 2009",

note = "2009 IEEE International Reliability Physics Symposium, IRPS 2009 ; Conference date: 26-04-2009 Through 30-04-2009",

}

Chiu, PY, Ker, M-D, Tsai, FY & Chang, YJ 2009, Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process. 於 2009 IEEE International Reliability Physics Symposium, IRPS 2009., 5173343, IEEE International Reliability Physics Symposium Proceedings, 頁 750-753, 2009 IEEE International Reliability Physics Symposium, IRPS 2009, Montreal, QC, Canada, 26/04/09. https://doi.org/10.1109/IRPS.2009.5173343

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AU - Chiu, Po Yen

AU - Ker, Ming-Dou

AU - Tsai, Fu Yi

AU - Chang, Yeong Jar

PY - 2009/11/12

Y1 - 2009/11/12

N2 - A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

AB - A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

KW - Electrostatic discharge (ESD)

KW - ESD clamp circuit

KW - Gate leakage

KW - Silicon-controlled rectifier (SCR)

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U2 - 10.1109/IRPS.2009.5173343

DO - 10.1109/IRPS.2009.5173343

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SN - 9780780388031

T3 - IEEE International Reliability Physics Symposium Proceedings

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BT - 2009 IEEE International Reliability Physics Symposium, IRPS 2009

T2 - 2009 IEEE International Reliability Physics Symposium, IRPS 2009

Y2 - 26 April 2009 through 30 April 2009

ER -

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

摘要

出版系列

Conference

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其它文件與鏈接

指紋

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