Two-step incremental analogue-to-digital converter

Chia-Hung Chen; Y. Zhang; Y. Jung; T. He; J. L. Ceballos; G. C. Temes

doi:10.1049/el.2013.0104

Two-step incremental analogue-to-digital converter

Chia-Hung Chen, Y. Zhang, Y. Jung, T. He, J. L. Ceballos, G. C. Temes

電機工程學系

研究成果: Article › 同行評審

15 引文斯高帕斯（Scopus）

摘要

A new incremental ADC (IADC) is proposed which extends the order of a conventional incremental ADC from N to (2N - 1) by way of a two-step operation. For a given conversion time, the duration of each step can be optimised. For an Nth-order IADC, the performance is equivalent to that of a (2N - 1)-order converter. However, it only needs the same circuitry as the Nth-order one. The new IADC is hence more accurate, and also much more power-efficient than the conventional ones.

原文	English
頁（從 - 到）	307-308
頁數	2
期刊	Electronics Letters
卷	49
發行號	4
DOIs	https://doi.org/10.1049/el.2013.0104
出版狀態	Published - 14 2月 2013

存取文件

10.1049/el.2013.0104

其它文件與鏈接

Link to publication in Scopus

引用此

@article{c47cece98a3849408cfce3efad1d150b,

title = "Two-step incremental analogue-to-digital converter",

abstract = "A new incremental ADC (IADC) is proposed which extends the order of a conventional incremental ADC from N to (2N - 1) by way of a two-step operation. For a given conversion time, the duration of each step can be optimised. For an Nth-order IADC, the performance is equivalent to that of a (2N - 1)-order converter. However, it only needs the same circuitry as the Nth-order one. The new IADC is hence more accurate, and also much more power-efficient than the conventional ones.",

author = "Chia-Hung Chen and Y. Zhang and Y. Jung and T. He and Ceballos, {J. L.} and Temes, {G. C.}",

year = "2013",

month = feb,

day = "14",

doi = "10.1049/el.2013.0104",

language = "English",

volume = "49",

pages = "307--308",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "4",

}

TY - JOUR

T1 - Two-step incremental analogue-to-digital converter

AU - Chen, Chia-Hung

AU - Zhang, Y.

AU - Jung, Y.

AU - He, T.

AU - Ceballos, J. L.

AU - Temes, G. C.

PY - 2013/2/14

Y1 - 2013/2/14

N2 - A new incremental ADC (IADC) is proposed which extends the order of a conventional incremental ADC from N to (2N - 1) by way of a two-step operation. For a given conversion time, the duration of each step can be optimised. For an Nth-order IADC, the performance is equivalent to that of a (2N - 1)-order converter. However, it only needs the same circuitry as the Nth-order one. The new IADC is hence more accurate, and also much more power-efficient than the conventional ones.

AB - A new incremental ADC (IADC) is proposed which extends the order of a conventional incremental ADC from N to (2N - 1) by way of a two-step operation. For a given conversion time, the duration of each step can be optimised. For an Nth-order IADC, the performance is equivalent to that of a (2N - 1)-order converter. However, it only needs the same circuitry as the Nth-order one. The new IADC is hence more accurate, and also much more power-efficient than the conventional ones.

UR - http://www.scopus.com/inward/record.url?scp=84877747506&partnerID=8YFLogxK

U2 - 10.1049/el.2013.0104

DO - 10.1049/el.2013.0104

M3 - Article

AN - SCOPUS:84877747506

SN - 0013-5194

VL - 49

SP - 307

EP - 308

JO - Electronics Letters

JF - Electronics Letters

IS - 4

ER -

Two-step incremental analogue-to-digital converter

摘要

存取文件

其它文件與鏈接

指紋

引用此