Two-staged parallel layer-aware partitioning for 3D designs

Yi Hang Chen, Yi Ting Chen, Juinn-Dar Huang

    研究成果: Paper同行評審

    摘要

    As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a parallel layer-aware partitioning algorithm, featuring both divergence stage and convergence stage, for TSV minimization in 3D structures. In the divergence stage, we employ OpenMP for the parallelization of 2-way min-cut partitioning and get the initial solution, and then refine it in the convergence stage. Experimental results show that the proposed two-staged algorithm can reduce the number of TSVs by up to 39% as compared to several existing methods.

    原文American English
    頁數4
    DOIs
    出版狀態Published - 28 4月 2014
    事件2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan
    持續時間: 28 4月 201430 4月 2014

    Conference

    Conference2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
    國家/地區Taiwan
    城市Hsinchu
    期間28/04/1430/04/14

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