Two experimental methods to characterize load capacitance of a CMOS gate

Kai Chen*, Chen-Ming Hu, Peng Fang, Min Ren Lin, Donald L. Wollesen

*此作品的通信作者

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

The load capacitance of a CMOS gate has been experimentally characterized by two independent methods on the particular wafers fabricated for this study Agreement between the two methods is obtained and confirmed using CMOS ring oscillators with gate oxide thicknesses from 2.5 to 5.8 nm and effective channel lengths down to 0.21 μm at voltages from 1.5 to 3.3 V. This study provides the capacitance data for an analytical gate delay model.

原文English
頁(從 - 到)773-775
頁數3
期刊Semiconductor Science and Technology
13
發行號7
DOIs
出版狀態Published - 1 七月 1998

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