Two dimensional nature of diffused line capacitance in the coplanar MOS LSI structure is investigated delineating importance of the side wall capacitance with decreasing feature size of devices. The effects of field channel stop ion implantation on the narrow channel effect, the field MOS threshold voltage and the junction breakdown voltage are also discussed toward optimization of coplanar process parameters.
|頁（從 - 到）||728-731|
|期刊||Technical Digest - International Electron Devices Meeting|
|出版狀態||Published - 1980|
|事件||Tech Dig Int Electron Devices Meet - Washington, DC, USA|
持續時間: 8 12月 1980 → 10 12月 1980