Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System with CMOS ICs under System-Level ESD Test

Yu Shu Shen, Ming Dou Ker, Hsin Chin Jiang

研究成果: Conference contribution同行評審

摘要

Transient voltage suppressor (TVS) has been widely used on the PCB to protect the microelectronics system against the system-level electrostatic discharge (ESD) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD test, if the TVS was designed with a holding voltage lower than the operating voltage of CMOS ICs those equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD test. By monitoring the transient voltage waveforms in the time domain during system-level ESD test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of TVS must be greater than the system operating voltage to keep the well signal integrity in the applications.

原文English
主出版物標題2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2020
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728161693
DOIs
出版狀態Published - 20 七月 2020
事件2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2020 - Singapore, Singapore
持續時間: 20 七月 202023 七月 2020

出版系列

名字Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
2020-July

Conference

Conference2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2020
國家/地區Singapore
城市Singapore
期間20/07/2023/07/20

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