Transient-induced latchup in CMOS technology: Physical mechanism and device simulation

Ming-Dou Ker*, Sheng Fu Hsu


    研究成果: Conference article同行評審

    9 引文 斯高帕斯(Scopus)


    The physical mechanism of transient-induced latchup (TLU) in CMOS ICs has been clearly characterized by device simulation and experimental verification in time domain perspective. An underdamped sine-wave-like voltage has been clarified as the real TLU-triggering stimulus under system-level electrostatic discharge (ESD) test. The specific "sweep-back" current caused by the minority carriers stored within the pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU.

    頁(從 - 到)937-940
    期刊Technical Digest - International Electron Devices Meeting, IEDM
    出版狀態Published - 1 12月 2004
    事件IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
    持續時間: 13 12月 200415 12月 2004


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