Transient-induced latchup in CMOS technology: Physical mechanism and device simulation

Ming-Dou Ker; Sheng Fu Hsu

doi:10.1109/IEDM.2004.1419338

Transient-induced latchup in CMOS technology: Physical mechanism and device simulation

Ming-Dou Ker^*, Sheng Fu Hsu

^*此作品的通信作者

研究成果: Conference article › 同行評審

9 引文斯高帕斯（Scopus）

摘要

The physical mechanism of transient-induced latchup (TLU) in CMOS ICs has been clearly characterized by device simulation and experimental verification in time domain perspective. An underdamped sine-wave-like voltage has been clarified as the real TLU-triggering stimulus under system-level electrostatic discharge (ESD) test. The specific "sweep-back" current caused by the minority carriers stored within the pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU.

原文	English
頁（從 - 到）	937-940
頁數	4
期刊	Technical Digest - International Electron Devices Meeting, IEDM
DOIs	https://doi.org/10.1109/IEDM.2004.1419338
出版狀態	Published - 2004
事件	IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States 持續時間: 13 12月 2004 → 15 12月 2004

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10.1109/IEDM.2004.1419338

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abstract = "The physical mechanism of transient-induced latchup (TLU) in CMOS ICs has been clearly characterized by device simulation and experimental verification in time domain perspective. An underdamped sine-wave-like voltage has been clarified as the real TLU-triggering stimulus under system-level electrostatic discharge (ESD) test. The specific {"}sweep-back{"} current caused by the minority carriers stored within the pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU.",

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AB - The physical mechanism of transient-induced latchup (TLU) in CMOS ICs has been clearly characterized by device simulation and experimental verification in time domain perspective. An underdamped sine-wave-like voltage has been clarified as the real TLU-triggering stimulus under system-level electrostatic discharge (ESD) test. The specific "sweep-back" current caused by the minority carriers stored within the pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU.

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M3 - Conference article

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JO - Technical Digest - International Electron Devices Meeting, IEDM

JF - Technical Digest - International Electron Devices Meeting, IEDM

Y2 - 13 December 2004 through 15 December 2004

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Transient-induced latchup in CMOS technology: Physical mechanism and device simulation

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