Timing and power fluctuations on gate-all-around nanowire CMOS circuit induced by various sources of random discrete dopants

Random dopant fluctuation (RDF) is one of fluctuation sources in sub-7-nm semiconductor technology node. In this paper, we estimate the timing and power fluctuations on 10-nm-gate gate-all-around (GAA) silicon nanowire (NW) complementary metal-oxide-semiconductor (CMOS) circuit induced by various random discrete dopants (RDDs) from channel (with/without doping), source/drain (S/D) extensions and penetration from S/D extensions. The 3D quantum mechanical transport and non-equilibrium Green's function (NEGF) models were used for the NW CMOS circuit. The experimentally validated device simulation indicates that at a similar threshold voltage, CMOS devices without channel doping possess 49.5% reduction on the normalized fluctuation of the static power consumption due to the reduction of σV_th and σI_off. The normalized fluctuation of dynamic power is comparable with/without channel doping due to small variation of the gate capacitance. Because of reduction of σI_sat, the normalized fluctuation of short-circuit power of CMOS circuit was reduced from 21.7% to 10.2% without channel doping. And, we found that the fluctuations of the timing, noise margin (NM) and power consumption of the NW CMOS circuit follow the trend of σV_th. From the point of view of N-/P-type NW MOSFETs caused by RDF, this study may show the fluctuation of CMOS circuit performance highly influenced by the key parameters of N-/P-type NW MOSFETs.