Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

Ya Shih Huang; Juinn-Dar Huang

doi:10.1109/ASQED.2010.5548228

Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

Ya Shih Huang^*, Juinn-Dar Huang

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based partitioning paradigm and is capable of keeping near-critical loops as physically close as possible to maximize system throughput. The experimental results show that the proposed placer achieves 4.57 times throughput improvement compared with a well-known simulated-annealing- based scheme.

原文	English
主出版物標題	Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010
頁面	134-139
頁數	6
DOIs	https://doi.org/10.1109/ASQED.2010.5548228
出版狀態	Published - 17 9月 2010
事件	2nd Asia Symposium on Quality Electronic Design, ASQED 2010 - Penang, 馬來西亞持續時間: 3 8月 2010 → 4 8月 2010

出版系列

名字	Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010

Conference

Conference	2nd Asia Symposium on Quality Electronic Design, ASQED 2010
國家/地區	馬來西亞
城市	Penang
期間	3/08/10 → 4/08/10

存取文件

10.1109/ASQED.2010.5548228

其它文件與鏈接

Link to publication in Scopus

引用此

Huang, Y. S., & Huang, J.-D. (2010). Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture. 於 Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010 (頁 134-139). 文章 5548228 (Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010). https://doi.org/10.1109/ASQED.2010.5548228

@inproceedings{cba1b1d918dc4f2f989e6cbafc7b57c6,

title = "Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture",

abstract = "As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based partitioning paradigm and is capable of keeping near-critical loops as physically close as possible to maximize system throughput. The experimental results show that the proposed placer achieves 4.57 times throughput improvement compared with a well-known simulated-annealing- based scheme.",

keywords = "Multicycle communication, Partition-based placement, Regular distributed architecture, Throughput-driven",

author = "Huang, {Ya Shih} and Juinn-Dar Huang",

year = "2010",

month = sep,

day = "17",

doi = "10.1109/ASQED.2010.5548228",

language = "English",

isbn = "9781424478088",

series = "Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010",

pages = "134--139",

booktitle = "Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010",

note = "2nd Asia Symposium on Quality Electronic Design, ASQED 2010 ; Conference date: 03-08-2010 Through 04-08-2010",

}

Huang, YS & Huang, J-D 2010, Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture. 於 Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010., 5548228, Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010, 頁 134-139, 2nd Asia Symposium on Quality Electronic Design, ASQED 2010, Penang, 馬來西亞, 3/08/10. https://doi.org/10.1109/ASQED.2010.5548228

Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture. / Huang, Ya Shih; Huang, Juinn-Dar.
Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010. 2010. p. 134-139 5548228 (Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

AU - Huang, Ya Shih

AU - Huang, Juinn-Dar

PY - 2010/9/17

Y1 - 2010/9/17

N2 - As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based partitioning paradigm and is capable of keeping near-critical loops as physically close as possible to maximize system throughput. The experimental results show that the proposed placer achieves 4.57 times throughput improvement compared with a well-known simulated-annealing- based scheme.

AB - As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based partitioning paradigm and is capable of keeping near-critical loops as physically close as possible to maximize system throughput. The experimental results show that the proposed placer achieves 4.57 times throughput improvement compared with a well-known simulated-annealing- based scheme.

KW - Multicycle communication

KW - Partition-based placement

KW - Regular distributed architecture

KW - Throughput-driven

UR - http://www.scopus.com/inward/record.url?scp=77956522547&partnerID=8YFLogxK

U2 - 10.1109/ASQED.2010.5548228

DO - 10.1109/ASQED.2010.5548228

M3 - Conference contribution

AN - SCOPUS:77956522547

SN - 9781424478088

T3 - Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010

SP - 134

EP - 139

BT - Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010

T2 - 2nd Asia Symposium on Quality Electronic Design, ASQED 2010

Y2 - 3 August 2010 through 4 August 2010

ER -

Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

摘要

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Conference

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指紋

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