With the advance of semiconductor manufacturing process technology, wire delay is gradually dominating system performance and becoming one of the most critical design issues. In this paper, we first show how interconnect latency incurred by wire delay degrades system throughput and re-examine several existing floorplanning strategies targeting this particular issue. Then we present a new throughput-aware floorplanner taking both quality and stability into account. It simultaneously optimizes a dynamic set of most performance-critical loops in a system to stably produce promising solutions. The experimental results demonstrate that our approach can double or even triple the system throughput in certain cases as compared with the prior arts.
|頁（從 - 到）||33-42|
|期刊||International Journal of Electrical Engineering|
|出版狀態||Published - 1 二月 2010|