Three-dimensional simulation of polysilicon thin film transistors with single-, double- and surrounding-gate structures

Yiming Li; Bo Shian Lee

Three-dimensional simulation of polysilicon thin film transistors with single-, double- and surrounding-gate structures

Yiming Li^*, Bo Shian Lee

^*此作品的通信作者

國立陽明交通大學

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

摘要

In this paper, a three-dimensional simulation of single-, double-, and surrounding-gate polysilicon thin film transistors (TFTs) is presented. Grain trap model is considered in the transport model. Calculations of the driving current, I_D-V_D and I_D-V_G curves are performed. Among three device structures, polysilicon TFTs with surrounding-gate structure reduce the leakage current and improve the short channel effects due to the excellent infinite-gate channel controllability.

原文	English
頁面	86-89
頁數	4
出版狀態	Published - 5月 2006
事件	2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States 持續時間: 7 5月 2006 → 11 5月 2006

Conference

Conference	2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
國家/地區	United States
城市	Boston, MA
期間	7/05/06 → 11/05/06

其它文件與鏈接

Link to publication in Scopus

引用此

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title = "Three-dimensional simulation of polysilicon thin film transistors with single-, double- and surrounding-gate structures",

abstract = "In this paper, a three-dimensional simulation of single-, double-, and surrounding-gate polysilicon thin film transistors (TFTs) is presented. Grain trap model is considered in the transport model. Calculations of the driving current, ID-VD and ID-VG curves are performed. Among three device structures, polysilicon TFTs with surrounding-gate structure reduce the leakage current and improve the short channel effects due to the excellent infinite-gate channel controllability.",

keywords = "Double-gate, Modeling and simulation, Polysilicon TFTs, Single-gate, Surrounding-gate",

author = "Yiming Li and Lee, {Bo Shian}",

year = "2006",

month = may,

language = "English",

pages = "86--89",

note = "2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings ; Conference date: 07-05-2006 Through 11-05-2006",

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TY - CONF

T1 - Three-dimensional simulation of polysilicon thin film transistors with single-, double- and surrounding-gate structures

AU - Li, Yiming

AU - Lee, Bo Shian

PY - 2006/5

Y1 - 2006/5

N2 - In this paper, a three-dimensional simulation of single-, double-, and surrounding-gate polysilicon thin film transistors (TFTs) is presented. Grain trap model is considered in the transport model. Calculations of the driving current, ID-VD and ID-VG curves are performed. Among three device structures, polysilicon TFTs with surrounding-gate structure reduce the leakage current and improve the short channel effects due to the excellent infinite-gate channel controllability.

AB - In this paper, a three-dimensional simulation of single-, double-, and surrounding-gate polysilicon thin film transistors (TFTs) is presented. Grain trap model is considered in the transport model. Calculations of the driving current, ID-VD and ID-VG curves are performed. Among three device structures, polysilicon TFTs with surrounding-gate structure reduce the leakage current and improve the short channel effects due to the excellent infinite-gate channel controllability.

KW - Double-gate

KW - Modeling and simulation

KW - Polysilicon TFTs

KW - Single-gate

KW - Surrounding-gate

UR - http://www.scopus.com/inward/record.url?scp=33845200643&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:33845200643

SP - 86

EP - 89

T2 - 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings

Y2 - 7 May 2006 through 11 May 2006

ER -

Three-dimensional simulation of polysilicon thin film transistors with single-, double- and surrounding-gate structures

摘要

Conference

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指紋

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