In this paper, a three-dimensional simulation of single-, double-, and surrounding-gate polysilicon thin film transistors (TFTs) is presented. Grain trap model is considered in the transport model. Calculations of the driving current, ID-VD and ID-VG curves are performed. Among three device structures, polysilicon TFTs with surrounding-gate structure reduce the leakage current and improve the short channel effects due to the excellent infinite-gate channel controllability.
|出版狀態||Published - 5月 2006|
|事件||2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States|
持續時間: 7 5月 2006 → 11 5月 2006
|Conference||2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings|
|期間||7/05/06 → 11/05/06|