A self-synchronized RF-interconnect (SSRFI), based on capacitive coupling and peak signal detection, is presented. In this SSRFI, small coupling capacitor (60fF) is used to interconnect vertical active layers in 3-Dimensional IC. The demonstrated SSRFI system, including both transmitter and receiver, has been designed, fabricated and verified in UMC 0.18μm CMOS with a PRBS data rate of 3Gbit/s, a BER of 1.2×10 -10 and a rms jitter of 1.28ps. The core circuit burns 4mW from a 1.8V supply and occupies 0.02mm 2 chip area.
|頁（從 - 到）||96-97|
|期刊||Digest of Technical Papers - Symposium on VLSI Technology|
|出版狀態||Published - 1 十月 2004|
|事件||2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States|
持續時間: 15 六月 2004 → 17 六月 2004