TY - GEN
T1 - Thin effective oxide thickness (∼0.5 nm) and low leakage current gate dielectric for Ge MOS devices by plasma nitrided Al2O3 intermediate layer
AU - Yang, Yi Gin
AU - Tsui, Bing Yue
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/6/3
Y1 - 2015/6/3
N2 - It is known that high dielectric constant (high-k) dielectric deposition on ultrathin GeO2 would damage the quality of GeO2 and degrade the interface. Both Al2O3 and AlN have been proposed as intermediate layer between high-k dielectric and GeO2, but the process has not been optimized. In this work, it is observed that the N2-plasma-nitrided Al2O3 is a good intermediate layer to suppress GeOx volatilization. Thin effective oxide thickness (∼0.5 nm), low leakage current (<4×10-2 A/cm2), and acceptable interface state density (∼4×1011 1/eV/cm2) have been demonstrated by the HfO2/N2-plasma-nitrided Al2O3/GeOx/Ge MIS structure.
AB - It is known that high dielectric constant (high-k) dielectric deposition on ultrathin GeO2 would damage the quality of GeO2 and degrade the interface. Both Al2O3 and AlN have been proposed as intermediate layer between high-k dielectric and GeO2, but the process has not been optimized. In this work, it is observed that the N2-plasma-nitrided Al2O3 is a good intermediate layer to suppress GeOx volatilization. Thin effective oxide thickness (∼0.5 nm), low leakage current (<4×10-2 A/cm2), and acceptable interface state density (∼4×1011 1/eV/cm2) have been demonstrated by the HfO2/N2-plasma-nitrided Al2O3/GeOx/Ge MIS structure.
UR - http://www.scopus.com/inward/record.url?scp=84940771998&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA.2015.7117579
DO - 10.1109/VLSI-TSA.2015.7117579
M3 - Conference contribution
AN - SCOPUS:84940771998
T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
BT - 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015
Y2 - 27 April 2015 through 29 April 2015
ER -