TY - GEN
T1 - Theoretical analysis for low-power test decompression using test-slice duplication
AU - Mu, Szu Pang
AU - Chao, Chia-Tso
PY - 2010/6/29
Y1 - 2010/6/29
N2 - This paper presents a single-test-input test-decompression scheme, named STSD, which utilize the technique of test-slice duplication to reduce the test-data volume as well as the signal transitions along scan paths. The encoding of STSD scheme focuses on maximizing the number of duplications made by a test-slice template. Mathematical models are also developed in this paper to estimate the compression ratio, test-application time, and scan-in transitions caused by STSD scheme, and in turn can further help designers to efficiently identify the best configuration of STSD scheme instead of going through a time-consuming simulation process. The experimental results based on large ISCAS and ITC benchmark circuits demonstrate the accuracy of the proposed mathematical models and the advantages of using STSD scheme.
AB - This paper presents a single-test-input test-decompression scheme, named STSD, which utilize the technique of test-slice duplication to reduce the test-data volume as well as the signal transitions along scan paths. The encoding of STSD scheme focuses on maximizing the number of duplications made by a test-slice template. Mathematical models are also developed in this paper to estimate the compression ratio, test-application time, and scan-in transitions caused by STSD scheme, and in turn can further help designers to efficiently identify the best configuration of STSD scheme instead of going through a time-consuming simulation process. The experimental results based on large ISCAS and ITC benchmark circuits demonstrate the accuracy of the proposed mathematical models and the advantages of using STSD scheme.
UR - http://www.scopus.com/inward/record.url?scp=77953910685&partnerID=8YFLogxK
U2 - 10.1109/VTS.2010.5469591
DO - 10.1109/VTS.2010.5469591
M3 - Conference contribution
AN - SCOPUS:77953910685
SN - 9781424466481
T3 - Proceedings of the IEEE VLSI Test Symposium
SP - 147
EP - 152
BT - Proceedings - 28th IEEE VLSI Test Symposium, VTS10
T2 - 28th IEEE VLSI Test Symposium, VTS10
Y2 - 19 April 2010 through 22 April 2010
ER -