Theoretical analysis for low-power test decompression using test-slice duplication

Szu Pang Mu*, Chia-Tso Chao


    研究成果: Conference contribution同行評審

    7 引文 斯高帕斯(Scopus)


    This paper presents a single-test-input test-decompression scheme, named STSD, which utilize the technique of test-slice duplication to reduce the test-data volume as well as the signal transitions along scan paths. The encoding of STSD scheme focuses on maximizing the number of duplications made by a test-slice template. Mathematical models are also developed in this paper to estimate the compression ratio, test-application time, and scan-in transitions caused by STSD scheme, and in turn can further help designers to efficiently identify the best configuration of STSD scheme instead of going through a time-consuming simulation process. The experimental results based on large ISCAS and ITC benchmark circuits demonstrate the accuracy of the proposed mathematical models and the advantages of using STSD scheme.

    主出版物標題Proceedings - 28th IEEE VLSI Test Symposium, VTS10
    出版狀態Published - 29 6月 2010
    事件28th IEEE VLSI Test Symposium, VTS10 - Santa Cruz, CA, United States
    持續時間: 19 4月 201022 4月 2010


    名字Proceedings of the IEEE VLSI Test Symposium


    Conference28th IEEE VLSI Test Symposium, VTS10
    國家/地區United States
    城市Santa Cruz, CA


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