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The Parasitic Latch-up Path from Substrate P+ Guard Ring to the NMOS in Deep N-Well Operating with Negative Voltage Sources
Zi Hong Jiang,
Ming Dou Ker
電子研究所
神經調控醫療電子系統研究中心
研究成果
:
Article
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同行評審
4
引文 斯高帕斯(Scopus)
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Keyphrases
NMOS
100%
Latch-up
100%
Deep N-well
100%
Negative Voltage
100%
Voltage Source
100%
Guard Ring
100%
CMOS Process
33%
P-type
16%
Electrical Stimulation
16%
Noise Reduction
16%
Series Resistance
16%
Operating Temperature
16%
Holding Voltage
16%
Positive-sequence Voltage
16%
Neuromodulation
16%
P Diffusion
16%
Isolation Ring
16%
Chip Layout
16%
Computer Science
Experimental Result
100%
Holding Voltage
100%
Series Resistance
100%
Medicine and Dentistry
Neuromodulation
100%
Electrotherapy
100%
Noise Reduction
100%
Engineering
Voltage Source
100%
Experimental Result
20%
Series Resistance
20%
Operating Temperature
20%
Holding Voltage
20%
Chip Layout
20%