原文 | English |
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專利號 | US 7,243,277 B2 |
出版狀態 | Published - 10 7月 2007 |
THE METHOD OF COMBINING MULTILEVEL MEMEORY CELLS FOR AN ERROR CORRECTION SCHEME
Jieh-Tsorng Wu (Inventor), Hsie-Chia Chang (Inventor), Ta-Hui Wang (Inventor)
研究成果: Patent
Jieh-Tsorng Wu (Inventor), Hsie-Chia Chang (Inventor), Ta-Hui Wang (Inventor)
研究成果: Patent
原文 | English |
---|---|
專利號 | US 7,243,277 B2 |
出版狀態 | Published - 10 7月 2007 |