The Implementation of a Reduced-Field Profile Design for High-Performance Bipolar Transistors

Pong Fei Lu, James H. Comfort, Denny D. Tang, B. S. Meyerson, J. Y.C. Sun

研究成果: Article同行評審

23 引文 斯高帕斯(Scopus)

摘要

This paper describes the first realization of a reduced-field design concept for advanced bipolar devices using the low-temperature epitaxial (LTE) technique to form the base layer. By inserting a lightly doped collector (LDC) spacer layer between the heavily doped base and collector regions, we have successfully demonstrated that the collector-base (CB) junction avalanche multiplication can be reduced substantially while maintaining high collector doping for current density consideration. Similar applications of the LDS technique to the emitter-base (EB) junction also result in a lower electric field, thus less EB junction reverse leakage.

原文English
頁(從 - 到)336-338
頁數3
期刊IEEE Electron Device Letters
11
發行號8
DOIs
出版狀態Published - 8月 1990

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