The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate

Tian-Li Wu*, Denis Marcon, Brice De Jaeger, Marleen Van Hove, Benoit Bakeroot, Dennis Lin, Steve Stoffels, Xuanwu Kang, Robin Roelofs, Guido Groeseneken, Stefaan Decoutere

*此作品的通信作者

研究成果: Conference contribution同行評審

38 引文 斯高帕斯(Scopus)

摘要

The selection of the gate dielectric is one of the most critical stability issues in recessed gate AlGaN/GaN transistors. In this work, we show that the quality of the gate dielectric has a strong impact on: 1) the threshold voltage (VTH) hysteresis, 2) the drain current reduction for enhancement mode devices, and 3) the forward gate bias TDDB (time dependent dielectric breakdown). It will be shown that the VTH hysteresis and the current reduction can be minimized by using a dielectric with lower interface state density (Dit) and less border traps, e.g., a PE-ALD SiN dielectric. Furthermore, the 0.01% failures at 20 years TDDB requirement at 150°C for a large power device, e.g., gate width Wg=36mm, necessitates the use of at least a 25nm-thick PE-ALD SiN gate dielectric.

原文English
主出版物標題2015 IEEE 27th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015
發行者Institute of Electrical and Electronics Engineers Inc.
頁面225-228
頁數4
ISBN(電子)9781479962594
DOIs
出版狀態Published - 12 6月 2015
事件27th IEEE International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015 - Hong Kong, China
持續時間: 10 5月 201514 5月 2015

出版系列

名字Proceedings of the International Symposium on Power Semiconductor Devices and ICs
2015-June
ISSN(列印)1063-6854

Conference

Conference27th IEEE International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015
國家/地區China
城市Hong Kong
期間10/05/1514/05/15

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