The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology

Steve S. Chung*, C. H. Yeh, S. J. Feng, C. S. Lai, J. J. Yang, C. C. Chen, Y. Jin, S. C. Chen, M. S. Liang

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    1 引文 斯高帕斯(Scopus)

    摘要

    In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFET for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the ID degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for thin gate oxide, the ID degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced VT shifts are significant, The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage current and an increase of ΔVT in thin-oxide with reduced width.

    原文English
    頁面279-282
    頁數4
    DOIs
    出版狀態Published - 7月 2004
    事件Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , 台灣
    持續時間: 5 7月 20048 7月 2004

    Conference

    ConferenceProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
    國家/地區台灣
    期間5/07/048/07/04

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