The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

Wei Jen Chang*, Ming-Dou Ker, Tai Xiang Lai, Tien Hao Tang, Kuan Cheng Su

*此作品的通信作者

    研究成果: Conference contribution同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.

    原文English
    主出版物標題Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007
    頁面249-252
    頁數4
    DOIs
    出版狀態Published - 1 12月 2007
    事件2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Bangalore, India
    持續時間: 11 7月 200713 7月 2007

    出版系列

    名字Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

    Conference

    Conference2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits
    國家/地區India
    城市Bangalore
    期間11/07/0713/07/07

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