The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

Wei Jen Chang; Ming-Dou Ker; Tai Xiang Lai; Tien Hao Tang; Kuan Cheng Su

doi:10.1109/IPFA.2007.4378094

The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

Wei Jen Chang^*, Ming-Dou Ker, Tai Xiang Lai, Tien Hao Tang, Kuan Cheng Su

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.

原文	English
主出版物標題	Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007
頁面	249-252
頁數	4
DOIs	https://doi.org/10.1109/IPFA.2007.4378094
出版狀態	Published - 1 12月 2007
事件	2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Bangalore, 印度持續時間: 11 7月 2007 → 13 7月 2007

出版系列

名字	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits
國家/地區	印度
城市	Bangalore
期間	11/07/07 → 13/07/07

存取文件

10.1109/IPFA.2007.4378094

其它文件與鏈接

Link to publication in Scopus

引用此

Chang, W. J., Ker, M.-D., Lai, T. X., Tang, T. H., & Su, K. C. (2007). The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. 於 Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007 (頁 249-252). 文章 4378094 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2007.4378094

Chang, Wei Jen ; Ker, Ming-Dou ; Lai, Tai Xiang 等. / The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. 頁 249-252 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{b87ab658198f4908b1929de6fd5e9bac,

title = "The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process",

abstract = "The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.",

author = "Chang, {Wei Jen} and Ming-Dou Ker and Lai, {Tai Xiang} and Tang, {Tien Hao} and Su, {Kuan Cheng}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/IPFA.2007.4378094",

language = "English",

isbn = "1424410142",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

pages = "249--252",

booktitle = "Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007",

note = "2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits ; Conference date: 11-07-2007 Through 13-07-2007",

}

Chang, WJ, Ker, M-D, Lai, TX, Tang, TH & Su, KC 2007, The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. 於 Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007., 4378094, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 頁 249-252, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Bangalore, 印度, 11/07/07. https://doi.org/10.1109/IPFA.2007.4378094

The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. / Chang, Wei Jen; Ker, Ming-Dou; Lai, Tai Xiang 等.
Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. p. 249-252 4378094 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

AU - Chang, Wei Jen

AU - Ker, Ming-Dou

AU - Lai, Tai Xiang

AU - Tang, Tien Hao

AU - Su, Kuan Cheng

PY - 2007/12/1

Y1 - 2007/12/1

N2 - The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.

AB - The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.

UR - http://www.scopus.com/inward/record.url?scp=39749120554&partnerID=8YFLogxK

U2 - 10.1109/IPFA.2007.4378094

DO - 10.1109/IPFA.2007.4378094

M3 - Conference contribution

AN - SCOPUS:39749120554

SN - 1424410142

SN - 9781424410149

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

SP - 249

EP - 252

BT - Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007

T2 - 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits

Y2 - 11 July 2007 through 13 July 2007

ER -

Chang WJ, Ker MD, Lai TX, Tang TH, Su KC. The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. 於 Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. p. 249-252. 4378094. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2007.4378094

The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

摘要

出版系列

Conference

存取文件

其它文件與鏈接

指紋

引用此