The generalized delay time and crosstalk models for the interconnect optimization design

Trent Gwo Yann Lee; Tseung-Yuen Tseng; Shyh Chyi Wong; Cheng Jer Yang; Mong Song Liang; Huang-Chung Cheng

The generalized delay time and crosstalk models for the interconnect optimization design

Trent Gwo Yann Lee^*, Tseung-Yuen Tseng, Shyh Chyi Wong, Cheng Jer Yang, Mong Song Liang, Huang-Chung Cheng

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研究成果 › 同行評審

摘要

New analytical models for estimating the delay time and crosstalk voltage with ramp input for isolated single line and coupled interconnect are presented here. Normal and crosstalk induced delay time deterioration and worst-case crosstalk noise models are given and verified by SPICE simulation. These models are accurate for various driver resistances, loading capacitances, and ramp waveforms. This paper is useful in the interconnect optimization design, the studies of delay time uncertainty due to noise and interconnect design in the worst case.

原文	American English
頁面	291-294
頁數	4
出版狀態	Published - 9月 2001
事件	9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems - Singapore, 新加坡持續時間: 3 9月 2001 → 5 9月 2001

Conference

Conference	9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems
國家/地區	新加坡
城市	Singapore
期間	3/09/01 → 5/09/01

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Lee, T. G. Y., Tseng, T.-Y., Wong, S. C., Yang, C. J., Liang, M. S., & Cheng, H.-C. (2001). The generalized delay time and crosstalk models for the interconnect optimization design. 291-294. 論文發表於 9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems, Singapore, 新加坡.

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title = "The generalized delay time and crosstalk models for the interconnect optimization design",

abstract = "New analytical models for estimating the delay time and crosstalk voltage with ramp input for isolated single line and coupled interconnect are presented here. Normal and crosstalk induced delay time deterioration and worst-case crosstalk noise models are given and verified by SPICE simulation. These models are accurate for various driver resistances, loading capacitances, and ramp waveforms. This paper is useful in the interconnect optimization design, the studies of delay time uncertainty due to noise and interconnect design in the worst case.",

author = "Lee, {Trent Gwo Yann} and Tseung-Yuen Tseng and Wong, {Shyh Chyi} and Yang, {Cheng Jer} and Liang, {Mong Song} and Huang-Chung Cheng",

year = "2001",

month = sep,

language = "American English",

pages = "291--294",

note = "9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems ; Conference date: 03-09-2001 Through 05-09-2001",

}

Lee, TGY, Tseng, T-Y, Wong, SC, Yang, CJ, Liang, MS & Cheng, H-C 2001, 'The generalized delay time and crosstalk models for the interconnect optimization design', 論文發表於 9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems, Singapore, 新加坡, 3/09/01 - 5/09/01 頁 291-294.

The generalized delay time and crosstalk models for the interconnect optimization design. / Lee, Trent Gwo Yann; Tseng, Tseung-Yuen; Wong, Shyh Chyi 等.
2001. 291-294 論文發表於 9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems, Singapore, 新加坡.

研究成果 › 同行評審

TY - CONF

T1 - The generalized delay time and crosstalk models for the interconnect optimization design

AU - Lee, Trent Gwo Yann

AU - Tseng, Tseung-Yuen

AU - Wong, Shyh Chyi

AU - Yang, Cheng Jer

AU - Liang, Mong Song

AU - Cheng, Huang-Chung

PY - 2001/9

Y1 - 2001/9

N2 - New analytical models for estimating the delay time and crosstalk voltage with ramp input for isolated single line and coupled interconnect are presented here. Normal and crosstalk induced delay time deterioration and worst-case crosstalk noise models are given and verified by SPICE simulation. These models are accurate for various driver resistances, loading capacitances, and ramp waveforms. This paper is useful in the interconnect optimization design, the studies of delay time uncertainty due to noise and interconnect design in the worst case.

AB - New analytical models for estimating the delay time and crosstalk voltage with ramp input for isolated single line and coupled interconnect are presented here. Normal and crosstalk induced delay time deterioration and worst-case crosstalk noise models are given and verified by SPICE simulation. These models are accurate for various driver resistances, loading capacitances, and ramp waveforms. This paper is useful in the interconnect optimization design, the studies of delay time uncertainty due to noise and interconnect design in the worst case.

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M3 - Paper

AN - SCOPUS:1842791410

SP - 291

EP - 294

T2 - 9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems

Y2 - 3 September 2001 through 5 September 2001

ER -

The generalized delay time and crosstalk models for the interconnect optimization design

摘要

Conference

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