New analytical models for estimating the delay time and crosstalk voltage with ramp input for isolated single line and coupled interconnect are presented here. Normal and crosstalk induced delay time deterioration and worst-case crosstalk noise models are given and verified by SPICE simulation. These models are accurate for various driver resistances, loading capacitances, and ramp waveforms. This paper is useful in the interconnect optimization design, the studies of delay time uncertainty due to noise and interconnect design in the worst case.
|出版狀態||Published - 9月 2001|
|事件||9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems - Singapore, Singapore|
持續時間: 3 9月 2001 → 5 9月 2001
|Conference||9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems|
|期間||3/09/01 → 5/09/01|