The generalized delay time and crosstalk models for the interconnect optimization design

Trent Gwo Yann Lee*, Tseung-Yuen Tseng, Shyh Chyi Wong, Cheng Jer Yang, Mong Song Liang, Huang-Chung Cheng

*此作品的通信作者

    研究成果: Paper同行評審

    摘要

    New analytical models for estimating the delay time and crosstalk voltage with ramp input for isolated single line and coupled interconnect are presented here. Normal and crosstalk induced delay time deterioration and worst-case crosstalk noise models are given and verified by SPICE simulation. These models are accurate for various driver resistances, loading capacitances, and ramp waveforms. This paper is useful in the interconnect optimization design, the studies of delay time uncertainty due to noise and interconnect design in the worst case.

    原文American English
    頁面291-294
    頁數4
    出版狀態Published - 9月 2001
    事件9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems - Singapore, Singapore
    持續時間: 3 9月 20015 9月 2001

    Conference

    Conference9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems
    國家/地區Singapore
    城市Singapore
    期間3/09/015/09/01

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