The first Ge nanosheets GAAFET CMOS inverters fabricated by 2D Ge/Si multilayer epitaxy, Ge/Si selective etching

Stacked Ge nanosheets (NSs) GAA FET CMOS inverters are demonstrated for the first time. In this work, for formation of well-defined stacked Ge NSs, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material for the following better selective etching between Ge/Si. In order to avoid island growth, Ge/Si multilayers must be grown at a low temperature. For selective etching, we found that, at a proper temperature, the Si layers can be easily etched away over Ge layers with good selectivity by TMAH solution. Additionally we found the dislocations in suspended Ge sheets are more easily to be removed than the case that Ge layers are still tied with Si layers. Finally, a functional Ge NSs GAAFET CMOS inverter with maximum voltage gain of 25V/V was demonstrated.